There are many requirements in CMOS technologies for circuits which are insensitive or less sensitive to process variations. An example of such a circuit is an output buffer circuit that reduces noise across process corners. FIG. 1 illustrates a conventional circuit 10 implementing such an output buffer circuit. The circuit 10 generally comprises a voltage reference block 12, a capacitor 14, a transistor MP1, a transistor MP2 and a transistor MN1. The voltage reference block 12 produces a signal VREF which generally controls the strength of the transistor MP1. During a condition when a high to low transition of the signal IN is received at the gates of the transistors MP2 and MN1, a low to high transition is generally presented at the node OUT. The signal at the node OUT is generally less sensitive to processing variations of the transistors MP1 and MP2. Examples of similar circuits may be found in U.S. Pat. No. 4,723,108.
Generally, the reference voltage block 12 draws a static direct current and tends to smooth the signal VREF. The capacitor 14 generally makes the circuit difficult to quickly turn on or off, which is a counterpart to compensating for processing variations. However, in applications of low power circuits or circuits where the static DC current must be zero, the voltage reference block 12 cannot be switched rapidly due to the smoothing effect of the capacitors. Certain circuits require only a reduction in process sensitivity rather than a full process correction, which presents options in circuit design.
FIG. 2 illustrates a conventional pulse generator circuit 30. The circuit 30 generally comprises a delay block 32, a NOR gate 34, an inverter 36, a NOR gate 38, an inverter 39 and an inverter 40. Other conventional delay circuits may include a chain of inverters or a chain of inverters driving RC networks. While the circuit 30 may provide a fixed amount of delay, it is generally not stable across process variations. It would be desirable to provide a reference circuit similar to that shown in FIG. 1 to provide a reduction in process sensitivity in circuits similar to the delay circuit shown in FIG. 2.